Inverter

One input, the opposite output: the simplest standard-cell example.

Open in the digital workspace Design record (JSON)

How it works

RTL states the Boolean function. The cell netlist chooses a physical library cell with a drive strength and a characterized delay.

Invert A in RTL.
Connect one sg13g2_inv_1 cell.
Use Logic check for the ideal function, then Cell transistors to inspect finite propagation delay.

Design decisions and limits

A larger drive cell usually trades more area and input capacitance for stronger output drive.
Delay depends on process, supply, temperature, input slew and output load.

Try it

Choose Cell transistors and compare typical, slow and fast device corners. Why are rise and fall delays different from each other and from the ideal zero-delay logic check?

Interface

Signal	Direction	Bits
`A`	input	1
`Y`	output	1

What runs in the browser

Logic check · Cell transistors · Gate delays · SPICE · mapped cells · 4 expected-output checks · 1 IHP cells in the explicit example

IHP SG13G2 130 nm. Open the workspace to run its checks, synthesize it and simulate its delays in your browser.