Designs › Digital › Digital logic
NAND gate
A two-input universal gate, checked against all four input combinations.
How it works
Y is low only when A and B are high. NAND is universal: combinations of NAND gates can realize any Boolean function.
- Enumerate all four Boolean input combinations.
- Map the function explicitly to one NAND2 cell.
- Inspect output transitions after input changes.
Design decisions and limits
- Input-to-output timing can differ between pins because the transistor paths differ.
- This truth-table test checks logic, not noise margins or transistor-level power.
Try it
Build an inverter by tying the NAND inputs together. What changes in input load?
Interface
| Signal | Direction | Bits |
|---|---|---|
A | input | 1 |
B | input | 1 |
Y | output | 1 |
What runs in the browser
Logic check · Cell transistors · Gate delays · SPICE · mapped cells · 8 expected-output checks · 1 IHP cells in the explicit example
IHP SG13G2 130 nm. Open the workspace to run its checks, synthesize it and simulate its delays in your browser.