Micropower two-stage op amp

How it works

A two-stage op amp for a power budget of about a microamp: a PMOS pair on an NMOS mirror, then a common-source NMOS stage, all run from a 100 nA reference. At these currents the signal devices sit near weak inversion, where g_m approaches I_D/(n·U_T) at fixed current. Bias current therefore strongly controls the bandwidth, but device size still affects inversion level, capacitance, output resistance and mismatch. One Miller capacitor across the second stage makes d2 the dominant pole; its nulling resistor, well above 1/g_m5, turns the Miller zero into phase lead above the crossover.

The testbench draws 100 nA out of the diode MB. MT, two copies of it, gives the pair 200 nA, and M6, N = 10 copies, gives the second stage 1 µA: 1.3 µA in all. M5 is N units with the mirror's W/L, so with the pair balanced it sinks M6's 1 µA at the same current density as M4 carries 100 nA: d2 rests at d1's 0.25 V and the output carries almost no systematic offset. The mirror is drawn at four times a unit's area, 1 × 8 µm, for matching.

Signal path

• Input pair (M1, M2, MT): MT's 200 nA divides between M1 and M2 as inp and inn differ; a rise on inp starves M2 and pulls d2 down.
• Mirror load (M3, M4): M3 turns M1's current into a gate voltage on d1 and M4 copies it onto d2, where both halves of the signal current meet.
• Second stage (M5, M6): M5, N units at the mirror's current density, amplifies d2 against M6, N copies of the bias unit, and inverts it onto out, so out follows inp.
• Compensation (Cc, Rz): Cc from d2 to out, multiplied by the second stage's gain, sets the dominant pole at d2; Rz in series moves the zero Cc makes into the left half-plane, above the crossover.

Key relations

• Transconductance: g_m ≈ I_D/(n·U_T). The weak-inversion limit these devices approach: the pair reaches g_m/I_D of 28, M5 about 19; U_T = kT/q is 26 mV at room temperature.
• Unity-gain frequency: f_u ≈ g_m1/(2π C_c) ≈ I_tail/(4π n U_T C_c). About 2.8 µS into 1.6 pF: 250 kHz. It approximately follows bias current while the input pair stays in weak inversion; sizing still affects inversion level and parasitic capacitance.
• Output pole: f_p2 ≈ g_m5/(2π C_L). 1 µA in M5 into 5 pF puts it near 620 kHz, 2.5 times the crossover. In the weak-inversion approximation both transconductances vary roughly as 1/U_T, helping their ratio track temperature. The model-based corner results check the remaining variation.
• Compensation zero: f_z = 1/[2π C_c (R_z − 1/g_m5)]. R_z is 150 kΩ against 1/g_m5 near 52 kΩ: the zero is in the left half-plane near 1 MHz and adds about 14° at the crossover.
• DC gain: A_0 ≈ g_m2 (r_o2 ∥ r_o4) · g_m5 (r_o5 ∥ r_o6). In both stages the NMOS r_o is the short one - M4 has only its 0.25 V V_GS across it - so the gain is about 69 dB, 64 dB hot.
• Nominal current balance: (W/L)_5/(W/L)_4 = N = (W/L)_6/(W/L)_B. M4 carries Ib and M6 sources N·Ib, so M5 is N units with M4's W/L.

Trade-offs

• Cc: larger lowers the unity-gain frequency and the slew rate, I_tail/C_c, and adds phase margin; smaller widens the bandwidth until the output pole, fixed by M5's 1 µA, catches up with it.
• N: more second-stage current raises g_m5 and pushes the output pole out, so a smaller Cc and a wider bandwidth become stable, at the cost of the supply current it multiplies.
• Rz: near 1/g_m5 the zero goes to infinity and gives nothing; much larger brings it down to the crossover, and Rz with M5's gate capacitance on d2 adds a pole of its own.
• A larger mirror (Wm, Lm) at the same W/L matches better - the offset falls from 2.5 to 1.4 mV σ and the worst supply rejection of 200 draws rises from 74 to 79 dB at 1 × 8 µm - but its gates load d1, the mirror's own pole, and the margin at the hot corner falls from 71° to 69°.
• Longer second-stage units (Ln) raise the gain only slowly - M4, not M5, has too little drain voltage - and their gate capacitance on d2 costs phase margin.

Testbenches and limits

• Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
• Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
• Step response: A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
• Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
• Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
• Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.
• Input common-mode range: Both inputs swept together while the output is held at one level. The range is where open-loop gain falls by no more than 6 dB and unity-gain frequency by no more than 5 % from their values at the design common mode; increases are allowed.
• Output swing: The amplifier as an inverting gain of one - its inverting input at the midpoint of the output and a signal, through two ideal controlled sources that load nothing - with the signal swept so the output crosses from rail to rail, and at each level the open-loop gain: the swing is where the gain stays within 6 dB of its value with the output at the input common mode.

Design variables and defaults

Ports

• inp input
• inn input
• out output
• vdd supply
• vss ground
• ib bias: the 100 nA reference, drawn out of this pin

Reference

J. Li, H. Zhi, R. Lyu, W. Li, Z. Bi, K. Zhu, Y. Zeng, W. Shan, C. Yan, F. Yang, Y. Li, X. Zeng, AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis, 2024. Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD '24), article 59, pp. 1-9.

The topology - a PMOS pair on an NMOS mirror, a common-source NMOS second stage, one Miller capacitor with a nulling resistor - and its micropower setting, a 100 nA reference. The weak-inversion sizing, the load, the compensation values and the spec targets are this library's.

• K. N. Leung and P. K. T. Mok, Analysis of Multistage Amplifier-Frequency Compensation, 2001