Two-stage Miller op amp, PMOS input

How it works

A general-purpose two-stage op amp whose input pair is PMOS, so its input range extends near ground. The nominal measured lower limit is about 34 mV under the bench's gain and bandwidth criteria. The pair, on an NMOS mirror, turns the differential input into a current and a voltage at d2; a wide NMOS common-source stage against a PMOS source multiplies that gain again and drives the output across most of the supply. A Miller capacitor across the second stage makes d2 the dominant pole, and a resistor in series with it keeps the second stage's feed-forward from costing phase.

The testbench draws the reference Ib (10 µA) out of the diode MB. MT is two copies of MB and feeds the pair with 2·Ib; M7 is N copies and feeds the second stage with N·Ib (100 µA at N = 10). With the pair balanced, M3 and M4 each carry Ib, half of the tail; M6 is N copies of that unit, so matched devices approximately balance the stage currents. Different drain voltages and random mismatch leave residual offset. The PMOS unit is wide, 24 µm, so that MT stays in saturation at the lowest supply and the hottest corner with the input common mode at 0.35 V: a starved tail is what lets the supply in.

Signal path

• Input pair (M1, M2, MT): MT's tail current divides between M1 and M2 as vinp and vinn differ; a rise on inp starves M2.
• Mirror load (M3, M4): M3 turns M1's current into a gate voltage and M4 copies it onto d2, where both halves of the signal current meet: d2 falls as inp rises.
• Second stage (M6, M7): M6, N copies of the load unit, amplifies d2 against M7, N copies of the bias unit, and inverts it onto out, so out follows inp.
• Compensation (Cc, Rz): Cc from d2 to out, multiplied by the second stage's gain, sets the dominant pole at d2 and pushes the output pole out; Rz above 1/g_m6 moves the zero Cc makes into the left half-plane.

Key relations

• DC gain: A_0 ≈ g_m1 (r_o2 ∥ r_o4) · g_m6 (r_o6 ∥ r_o7). Two stages, each a transconductance into its own output resistance.
• Unity-gain frequency: ω_u ≈ g_m1/C_c. Set by the input pair and the Miller capacitor, not by the load.
• Output pole: ω_p2 ≈ g_m6/C_L. It must sit well above ω_u for a good phase margin: here about three times.
• Compensation zero: ω_z = 1/[C_c (1/g_m6 − R_z)]. Negative, in the left half-plane, once R_z > 1/g_m6.
• Nominal current balance: (W/L)_6/(W/L)_4 = 2·(W/L)_7/(W/L)_T. Met by copies: M6 = N units, M7 = N units, MT = 2 units - both sides equal N.

Trade-offs

• Cc: larger lowers ω_u and slows the step, but adds phase margin; smaller widens the bandwidth until the output pole catches up with it.
• N: more second-stage current raises g_m6, pushing the output pole out and the slew into the load up, at the cost of supply current.
• Longer devices (L1, Ln, Lp) raise every r_o and the gain, but add capacitance at d2 and at the output, pulling the output pole in.
• Rz: too small leaves the zero in the right half-plane; much larger than 1/g_m6 brings the zero down towards ω_u, where it can lift the gain curve back up.

Testbenches and limits

• Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
• Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
• Step response: A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
• Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
• Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
• Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.
• Input common-mode range: Both inputs swept together while the output is held at one level. The range is where open-loop gain falls by no more than 6 dB and unity-gain frequency by no more than 5 % from their values at the design common mode; increases are allowed.
• Output swing: The amplifier as an inverting gain of one - its inverting input at the midpoint of the output and a signal, through two ideal controlled sources that load nothing - with the signal swept so the output crosses from rail to rail, and at each level the open-loop gain: the swing is where the gain stays within 6 dB of its value with the output at the input common mode.

Design variables and defaults

Ports

• inp input
• inn input
• out output
• vdd supply
• vss ground
• ib bias: the reference current, drawn out of this pin

Reference

B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2016. Sec. 9.3 (two-stage op amps) and Sec. 10.5 (compensating them).

The topology - a PMOS pair on an NMOS mirror, an NMOS common-source second stage - and Miller compensation with a nulling resistor. The sizing is this library's, for SG13G2 at 1.2 V.