Two-stage Miller OTA

How it works

A two-stage OTA for more gain than one SG13G2 stage gives: a five-transistor first stage drives a common-source second stage, so the two gains multiply. Two high-impedance nodes mean two low poles, so C_c, bridging the second stage, splits them: Miller multiplication makes n2 dominant while the output pole moves out. C_c also feeds n2 forward to the output, a right-half-plane zero; R_z in series moves it away.

I_bias, 20 µA by default, is supplied externally into the bn port and sets its voltage through the diode-connected Mb; Mt copies it as the tail, and M6, N6 copies of Mb, sinks N6·I_bias. M5, N5 copies of a load device carrying I_bias/2, sources N5·I_bias/2, so the stages agree only when N5 = 2·N6, as the defaults 8 and 4 do.

Signal path

• Input pair (M1, M2): Splits the tail current by the input difference. A rise on inp pulls n2 down through M2; the second stage inverts it back, so the output follows inp.
• Mirror load (M3, M4): M3 turns M1's current into the gate voltage n1; M4 copies it onto n2, where both halves of the signal current add.
• Second stage (M5, M6): M5, a common-source PMOS driven from n2, amplifies and inverts against the mirrored sink M6, which sets its current.
• Compensation (Cc, Rz): Cc from the output back to n2 is multiplied by the second stage's gain, making n2 the dominant pole; Rz sets where Cc's feed-forward zero lands.

Key relations

• DC gain: A_0 ≈ g_m1 (r_o2 ∥ r_o4) · g_m5 (r_o5 ∥ r_o6). In each stage the NMOS r_o is the smaller one and sets the gain.
• Unity-gain frequency: GBW ≈ g_m1/(2π·C_c). Set by the input pair and C_c, 1.5 pF by default; C_L barely enters while ω_p2 stays above it.
• Output pole: ω_p2 ≈ g_m5/C_L. About 2.2 times the unity-gain frequency gives 60° of margin if any right-half-plane zero is ten times out.
• Miller zero: ω_z = 1/[C_c (1/g_m5 − R_z)]. A right-half-plane zero while R_z < 1/g_m5; the default 3 kΩ exceeds that and puts it in the left half plane, near 50 MHz, where it gives phase back at the crossover. The published minimum 60° phase margin is checked numerically at each qualification condition.
• Current balance: N5·I_bias/2 = N6·I_bias ⇒ N5 = 2·N6. Break it and n2 moves until M5 carries what M6 sinks: offset closed-loop, a railed output open.

Trade-offs

• Raising C_c lowers the unity-gain frequency and the slew rate, I_bias/C_c, and buys phase margin by pulling the crossover further below g_m5/C_L.
• Setting R_z to 0 leaves the right-half-plane zero g_m5/C_c, which subtracts phase where the gain crosses 0 dB; a few kΩ turns it into lead.
• Raising N5 and N6 together, keeping N5 = 2·N6, raises g_m5 and pushes the output pole out, for more margin at more supply current.
• Raising I_bias raises g_m1, the bandwidth and the slew rate, but shortens every r_o: DC gain falls as supply current rises.

Testbenches and limits

• Open-loop response

Design variables and defaults

Ports

• inp input (+)
• inn input (-)
• out output
• bn bias: inject I_b into Mb's diode-connected node; the core mirrors this externally supplied reference current
• vdd supply
• 0 ground

Reference

P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 3rd ed., Oxford University Press, 2012. CMOS Operational Amplifiers - the two-stage op amp and its design procedure.

The topology, the current-matching rule between the two stages, and the nulling resistor in series with the Miller capacitor.

• B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., 2017