Five-transistor OTA, PMOS input

How it works

The five-transistor OTA with its pair in PMOS. M1 and M2 split the tail current by the input difference; the NMOS mirror M3–M4 copies M1's share onto the output, where M2 delivers its own, so the two halves of the signal current add in the output resistance. The pair's drains sit only a mirror V_GS above ground while its sources sit a V_SG above the input, so the input can go down to ground - the range an NMOS pair gives up. The output is the only high-impedance node, and the load capacitance is the whole compensation.

The testbench draws the 10 µA reference out of the diode MB; MT is K = 2 copies of it and feeds the pair with 20 µA, 10 µA a side, which puts the wide pair near weak inversion (g_m/I_D about 18). The mirror is sized to sit at 0.33 V, next to the 0.35 V design common mode: with the output there, M3 and M4 have the same V_DS and the output carries almost no systematic offset.

Signal path

• Input pair (M1, M2, MT): MT's tail current divides between M1 and M2 as inp and inn differ. inp drives M1, on the mirror's diode side: a rise there starves M1, so out follows inp.
• Mirror load (M3, M4): M3 turns M1's current into a gate voltage on d1, and M4 copies that current onto out.
• Output node (M2, M4): M2's current and M4's copy move in opposite directions, so the whole signal current flows into r_o2 ∥ r_o4 and into C_L.

Key relations

• DC gain: A_0 ≈ g_m2 (r_o2 ∥ r_o4). M4's r_o is the short one - an SG13G2 core NMOS reaches g_m/g_ds of about 33 at this length and drain voltage, the PMOS pair about 180 - so the gain is near 31 dB.
• Unity-gain frequency: f_u ≈ g_m1/(2π C_L). About 0.18 mS into 1 pF and the output's own capacitance: 26 MHz.
• Lowest input: V_CM,min = V_GS3 + V_DSAT1 − V_SG1. M1 stays saturated while its drain, at the mirror's V_GS, is a V_DSAT below its source. 0.33 + 0.13 − 0.47 V is just below zero: the range reaches ground.
• Highest input: V_CM,max = V_DD − V_SG1 − V_DSAT,T. The tail source needs its own V_DSAT; above this its current, and with it g_m1 and the bandwidth, falls.
• Output swing: V_DSAT4 ≤ v_out ≤ V_tail − V_DSAT2. About 0.16 V to 0.68 V with the input at 0.35 V: as a buffer the output cannot follow the input all the way to ground.
• Slew rate: SR = I_tail/C_L. The large-signal limit, with the pair fully steered. The step bench's 0.2 V step is mostly linear settling on the 6 ns time constant and reads about half of it.

Trade-offs

• A wider NMOS mirror lowers its V_GS and extends the input range towards ground, but lowers r_o4 per µA and the gain with it: at 3.6 µm, with the common mode at 0.4 V, the gain was 32.5 dB and the range stopped 0.14 V above ground hot.
• A longer NMOS mirror raises r_o4 and the gain, but loads d1 with gate capacitance: at 4 µm the mirror pole came down near the crossover and the phase margin fell below 70°.
• More tail current (K) raises g_m1, the bandwidth and the slew rate, and takes the pair out of weak inversion, raising V_SG1: the input range gains at the bottom and loses at the top.
• A wider input pair lowers the offset and adds g_m per µA, but lowers V_SG1, which the input range at ground depends on, and adds input capacitance.

Testbenches and limits

• Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
• Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
• Step response: A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
• Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
• Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
• Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.
• Input common-mode range: Both inputs swept together while the output is held at one level. The range is where open-loop gain falls by no more than 6 dB and unity-gain frequency by no more than 5 % from their values at the design common mode; increases are allowed.
• Output swing: The amplifier as an inverting gain of one - its inverting input at the midpoint of the output and a signal, through two ideal controlled sources that load nothing - with the signal swept so the output crosses from rail to rail, and at each level the open-loop gain: the swing is where the gain stays within 6 dB of its value with the output at the input common mode.

Design variables and defaults

Ports

• inp input
• inn input
• out output
• vdd supply
• vss ground
• ib bias: the reference current, drawn out of this pin

Reference

H. Pretl, M. Koefinger, S. Dorrer, Analog Circuit Design, Institute for Integrated Circuits, Johannes Kepler University Linz / Zenodo, 2024. Open course material for the IHP SG13G2 130 nm PDK (https://github.com/iic-jku/analog-circuit-design).

The topology - a differential pair, a current-mirror load and a tail source - and the g_m/I_D sizing method the course teaches in SG13G2. The PMOS input, chosen for an input range that reaches ground, and the sizing are this library's.