Five-transistor OTA

How it works

The smallest useful OTA: it turns the voltage difference between inp and inn into a current and, in its own output resistance, into a single-ended output voltage. The pair M1–M2 splits the tail current by the input difference; the mirror M3–M4 copies M1's current onto the output, where M2 draws its own, so the two equal and opposite signal changes add. The output is the only high-impedance node, so C_L sets the bandwidth directly and the default load supplies the needed dominant-pole compensation.

I_bias, 20 µA by default, enters the external bn port and sets the gate voltage of the diode-connected Mb, and Mt, the same size, copies it as the tail current, so each branch carries I_bias/2 at balance. Mb, Mt and the NMOS bodies return to the ground port. In the open-loop bench a DC-only feedback path holds the output at V_CM, 0.6 V by default.

Signal path

• Input pair (M1, M2): Splits the tail current by the input difference. inp drives M1, on the mirror's diode side, so the output follows inp.
• Current-mirror load (M3, M4): M3 turns M1's current into a gate voltage on n1; M4 copies that current onto the output.
• Output node (M2, M4): M4's copy and M2's current move in opposite directions, so the whole signal current flows into the output resistance and C_L.

Key relations

• DC gain: A_0 ≈ g_m1 (r_o2 ∥ r_o4). M2's r_o is the short one: SG13G2 core NMOS reach far lower g_m/g_ds than the PMOS load.
• Unity-gain frequency: GBW ≈ g_m1/(2π·C_L). Four times C_L is a quarter of the bandwidth; the DC gain does not move.
• Dominant pole: ω_p1 ≈ 1/[(r_o2 ∥ r_o4)·C_L]. The output is the only high-impedance node, so this pole dominates.
• Mirror pole: ω_p2 ≈ g_m3/C_n1. Half the signal bypasses n1, giving a zero at 2·ω_p2; lighter loads push the crossover towards it.
• Slew rate: SR = I_tail/C_L. The pair is fully steered during a large step; measured lower, as the output also carries device capacitance.

Trade-offs

• Doubling C_L halves the unity-gain frequency and the slew rate and adds phase margin; the DC gain does not move.
• A longer L input pair raises r_o2, the resistance that limits the gain, but lowers g_m1 at fixed width and adds input capacitance.
• Raising I_bias raises g_m1, bandwidth and slew rate together, but shortens every r_o, so the DC gain falls a little.
• Widening W input pair moves the pair towards weak inversion: more g_m1 per µA and less offset from mismatch, but more capacitance on the inputs.

Testbenches and limits

• Open-loop response
• Unity-gain step

Design variables and defaults

Ports

• inp input (+)
• inn input (-)
• out output
• bn bias: inject I_b into Mb's diode-connected node; the tail mirrors this externally supplied reference current
• vdd supply
• 0 ground: NMOS substrate and bias-current return

Reference

P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Wiley, 2009. the single-stage differential amplifier with an active current-mirror load.

The topology and the results this bench measures: A0 = gm1*(ro2||ro4), a dominant pole at the output, and a slew rate of I_tail/C_L.