Folded-cascode OTA

How it works

A single-stage OTA that reaches cascode output resistance without stacking cascodes on its input pair, so the input range and the output swing no longer compete for the same volts. The PMOS pair M1–M2 pushes its signal current down into the fold nodes f1 and f2, where NMOS common-gate devices M5–M6 carry it up to a cascoded PMOS mirror that recombines both halves at out. The output is the only high-impedance node, so the load sets the dominant pole. At 1.2 V the design is a headroom budget: both cascode gates are generated on chip, each from a copy of the cascode it biases, so they track process, supply and temperature.

Only the 10 µA reference comes from outside, drawn out of the diode MB. MT, four copies, gives the pair 20 µA a side; MB1 and MB2 copy it into the NMOS reference MN and into the stack MCN–MZN, and MN2 draws it through MCP–MZP. The sinks M3 and M4 are four copies of MN, so 20 µA is left for each cascode branch: 120 µA in all. MCN is one unit of the cascodes M5–M6 and MCP one of M9–M10, at their current density.

Signal path

• Input pair (M1, M2, MT): MT's 40 µA divides between M1 and M2 as inp and inn differ, and each drain delivers its share to a fold node. A rise on inp cuts M1's current.
• Folding sinks (M3, M4): Each draws a fixed 40 µA from its fold node, so whatever an input device stops delivering, the cascode above it must: the signal current reverses direction and folds upwards.
• NMOS cascodes (M5, M6): Common-gate at cn: they pass the current changes up to gp and out while holding the fold nodes, low-impedance, almost still.
• Cascode mirror (M7, M8, M9, M10): M7 and M8 take their gates from gp, M9's drain, so M5's current is copied through M10 onto out, where M6 draws its own: a rise on inp raises M5's current and out.
• Cascode bias (MCN, MZN, MCP, MZP): Each cascode gate is a cascode unit's V_GS (MCN, MCP) above the drop across a device held in triode (MZN, MZP): the fold nodes sit at MZN's drop and the mirror's drains at MZP's.

Key relations

• DC gain: A_0 ≈ g_m1 · {[g_m6 r_o6 (r_o4 ∥ r_o2)] ∥ [g_m10 r_o10 r_o8]}. The NMOS side is the smaller, about 1 MΩ against 20 MΩ: M6's g_m/g_ds is only 23 with 0.3 V across it, and the sink has 0.2 V. About 52 dB.
• Unity-gain frequency: f_u ≈ g_m1/(2π C_L). 0.36 mS into 2 pF and the output's own capacitance: 27 MHz.
• Output swing: V_DS,MZN + V_DSAT6 ≤ v_out ≤ V_DD − V_SD,MZP − V_DSAT10. Two saturation voltages at each end: 0.30 V to 0.84 V at 27 °C, 0.38 V to 0.67 V slow, hot and with the supply 10 % low.
• PMOS mirror window: V_DSAT7 ≤ V_SD,MZP ≤ V_SG7 − V_DSAT9. Where M7 and M9 are both saturated: 0.23 V wide at 27 °C, 0.12 V hot, and MZP's drop - 0.29 V, 0.34 V hot - sits in it at every corner.
• Highest input: V_CM,max = V_DD − V_DSAT,T − V_SG1. With the pair's n-well on its source V_SG1 is 0.41 V rather than 0.46 V: the range reaches 0.67 V, 0.56 V at the worst corner.
• Slew rate: SR = I_tail/C_L. Holds because each sink draws the whole tail current, so no fold node is ever left without a path.

Trade-offs

• The design common mode must sit in the buffer's window, above the output's floor and under the pair's ceiling: 0.38 V to 0.56 V at the slow, hot, low-supply corner, which is why it is 0.5 V and the step only 0.1 V.
• Longer NMOS cascodes raise the gain, 55 dB at 2 µm, but raise their V_DSAT and lift the output's floor to where M6 reaches the edge of saturation hot.
• A wider MZN lowers its drop: more room at the bottom of the output swing, less under the folding sinks - and they are the devices whose V_DSAT grows most hot.
• More tail current (H) raises g_m1 and the bandwidth, but the sinks must grow with it (C ≥ H for slewing), and their extra current lowers their r_o and the gain.

Testbenches and limits

• Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
• Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
• Step response: A 100mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
• Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
• Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
• Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.
• Input common-mode range: Both inputs swept together while the output is held at one level. The range is where open-loop gain falls by no more than 6 dB and unity-gain frequency by no more than 5 % from their values at the design common mode; increases are allowed.
• Output swing: The amplifier as an inverting gain of one - its inverting input at the midpoint of the output and a signal, through two ideal controlled sources that load nothing - with the signal swept so the output crosses from rail to rail, and at each level the open-loop gain: the swing is where the gain stays within 6 dB of its value with the output at the input common mode.

Design variables and defaults

Ports

• inp input
• inn input
• out output
• vdd supply
• vss ground
• ib bias: the reference current, drawn out of this pin

Reference

M. Scherzer, M. Auer, CORA-OpAmp: A Compact Open-Source Reinforcement-Learning Approach for Operational Amplifier Optimization in IHP SG13G2, 2025. 2025 32nd IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 1-4.

The topology that paper sizes in SG13G2: a PMOS pair folding into NMOS sinks, NMOS cascodes, and a PMOS cascode mirror whose gates hang on its cascode's drain. The on-chip cascode biases, the headroom budget, the sizing and the spec targets are this library's.