Telescopic-cascode OTA

How it works

A single-stage OTA that cascodes both the pair and the mirror of the five-transistor OTA in one stack, multiplying the output resistance - and so the gain - by g_m·r_o on each side without spending any extra current. The price is headroom: tail, input device, NMOS cascode, PMOS cascode and mirror stand in series between the rails. At 1.2 V the output keeps every device saturated only between about 0.53 V and 0.90 V, and as a unity-gain buffer, with the output at the input, the input device and its cascode must share one V_GS. The cascode gates are generated on chip: the NMOS one stands on the tail node so it follows the input.

The testbench feeds the 5 µA reference into the diode MB. MT, five copies of it, carries 25 µA: about 6 µA through the bias stack MCN–MZC, which MPC feeds from the PMOS reference MP, and 9.4 µA to each input device. MN1 and MN2 run about a fifth above Ib, their drains far above MB's. The pair is short (0.5 µm) and strongly inverted so its V_GS, about 0.47 V, has room for its own V_DSAT and its cascode's; the cascodes, tail and mirror run near weak inversion, where their V_DSAT is smallest. 42 µA in all.

Signal path

• Input pair (M1, M2, MT): MT's current, less the Ib its bias stack takes, divides between M1 and M2 by inp − inn. inp drives M1, under the mirror's diode side, so out follows inp.
• NMOS cascodes (M3, M4): Common-gate at cn: they pass the pair's current changes up unchanged and hold the pair's drains d1 and d2 almost still, multiplying the NMOS side's resistance by g_m4 r_o4.
• Cascode mirror (M5, M6, M7, M8): M7 and M8 take their gates from gp, M5's drain, so M1's current is copied through M6 onto out, where M4 draws M2's.
• Cascode bias (MCN, MZC, MCP, MZP): cn is a cascode unit's V_GS (MCN) above the drop across MZC, whose source is the tail node, so the pair's drains ride with the input; cp is a PMOS cascode unit's V_SG (MCP) below the drop across MZP, in triode under vdd.

Key relations

• DC gain: A_0 ≈ g_m1 · [(g_m4 r_o4 r_o2) ∥ (g_m6 r_o6 r_o8)]. The NMOS side is the smaller, about 4 MΩ against 24 MΩ: the short input device has g_m/g_ds near 15. About 52 dB.
• Unity-gain frequency: f_u ≈ g_m1/(2π C_L). 0.1 mS into 2 pF: 7.5 MHz.
• Buffer headroom: V_DS1 + V_DS4 = V_GS1 ≥ V_DSAT1 + V_DSAT4. With the output at the input, the pair and its cascode share one V_GS. Hot the threshold falls 70 mV while both V_DSAT grow, which is why the pair is short and strongly inverted.
• Output swing: V_tail + V_DS1 + V_DSAT4 ≤ v_out ≤ V_DD − V_SD,MZP − V_DSAT6. With the input at 0.66 V: 0.53 V to 0.90 V at 27 °C, 0.57 V to 0.75 V slow, hot and 10 % low - under 0.2 V.
• Mirror-side headroom: V_tail + V_DS1 + V_DSAT3 ≤ V_DD − V_SG7. M3's drain is the mirror's gate line gp. With the tail's own V_DSAT under it this sets the stack: the one common mode that serves every corner is about 0.66 V.
• Slew rate: SR = I_pair/C_L. The pair's 19 µA into 2 pF is about 9 V/µs; the 0.1 V step barely steers the pair and reads 2 V/µs.

Trade-offs

• The input pair's size is set by headroom, not by noise or matching: at 1.2 × 0.5 µm it gives about 930 nV/√Hz at 1 kHz and an offset near 8 mV σ. Longer, it would lose threshold; wider, V_GS - either takes M4 out of saturation hot.
• Longer NMOS cascodes raise g_m4 r_o4 and the gain at no headroom cost, since their gate comes from a unit of their own: 2 µm gives 51.6 dB against 49.6 dB at 1 µm.
• A wider MZC lowers the pair's drain voltage: more room for M4 and for M3 on the mirror side, less for the input devices.
• More current per branch (C) raises g_m1 and the bandwidth and lets the pair grow in area at the same inversion, at the cost of supply current; the bias stacks stay at one Ib.

Testbenches and limits

• Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
• Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
• Step response: A 100mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
• Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
• Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
• Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.
• Input common-mode range: Both inputs swept together while the output is held at one level. The range is where open-loop gain falls by no more than 6 dB and unity-gain frequency by no more than 5 % from their values at the design common mode; increases are allowed.
• Output swing: The amplifier as an inverting gain of one - its inverting input at the midpoint of the output and a signal, through two ideal controlled sources that load nothing - with the signal swept so the output crosses from rail to rail, and at each level the open-loop gain: the swing is where the gain stays within 6 dB of its value with the output at the input common mode.

Design variables and defaults

Ports

• inp input
• inn input
• out output
• vdd supply
• vss ground
• ib bias: the reference current, fed into this pin

Reference

B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd, McGraw-Hill, 2016. Sec. 11.5.1 'Telescopic Op Amp' (p. 473); the topology is introduced in Ch. 9 'Operational Amplifiers', Sec. 9.2 'One-Stage Op Amps'.

The topology - an NMOS pair with NMOS cascodes under a cascoded PMOS mirror whose gates hang on its cascode's drain - and the headroom analysis of a telescopic stage in unity-gain feedback. The on-chip cascode biases, the one that stands on the tail node, the sizing and the spec targets are this library's.