Three-stage op amp, active zero, cross feedforward

How it works

A three-stage op amp compensated by one capacitor returned through the first stage's regulated cascode, with an active-zero mirror in the second stage and two feedforward paths: the output device on the first stage's output, and the second stage's load on the first stage's mirror node. The load makes the second stage slow, which keeps the loop the capacitor closes well damped. The input pair and the source and sink units use extra area for common-mode matching, while the two regulator transistors keep separate, smaller geometry so their local poles stay fast.

The testbench draws Ib (2.5 µA) out of MB. MT is one copy, each 2 µm input device carries half an Ib, and the 8 µm sink units leave 1.5 Ib for each cascode. The regulators MA1 and MA2 use dedicated 4 µm units, fed by a two-unit 4 µm PMOS source MR through Rr1 and Rr2 (200 kΩ); separating them from the 8 µm signal units preserves the regulator poles. M7/M8 are three units each and M12 one, so the second stage runs at 1.27 µA, and M14, thirty-two copies of M9, gives the output 40 µA.

Signal path

• First stage (M1, M2, MT, M3, M4, M5, M6, MA1, MA2, Rr1, Rr2, MR, M7, M8): The PMOS pair M1/M2 on the tail MT folds into the sinks M3/M4 and the cascodes M5/M6. Each cascode's gate is driven by a regulator, MA1 or MA2, off its own source and loaded by Rr1 or Rr2 from the source MR, so the folding nodes f1, f2 are held at the regulators' V_GS and look into a resistance several times lower. The mirror M7/M8 gives the output o1.
• Second stage, active zero (M9, M10, Rz2, M11): M9 turns o1 into a current into the diode M10, gated from d2 through Rz2; M11 mirrors it onto o2, with a gain that rises where the mirror's pole would fall.
• Cross feedforward (M12, M7): M12, one of the three units the mirror M7/M8 is built from, gated by x1, loads o2 and adds the first stage's signal to it in phase.
• Output stage (M13, M14): M13 on o2 sinks and M14 on o1 sources: a push-pull output, and M14, thirty-two copies of M9, is the feedforward path from o1 to the output. Both paths invert, so out follows inp.
• Miller capacitor (Cm, M6): Cm injects the output's current into f2, the regulated cascode M6's source, which carries it to o1 and sets the dominant pole.

Key relations

• DC gain: A_0 ≈ g_m1 R_o1 · g_m9 R_o2 · g_m13 R_o3. R_o1 is set mostly by the mirror M8, R_o2 and R_o3 by the NMOS M11 and M13, whose V_A is only 2-3 V: the reason those two are long.
• Unity-gain frequency: ω_u ≈ g_m1/C_m. About 3.6 MHz with Cm at 1.3 pF.
• Buffer resistance: r_x ≈ 1/(g_m6 (1 + g_m,MA2 R_r)). The 4 µm regulator unit and 200 kΩ load give a local gain near six without the capacitance of the 8 µm sink unit; the current buffer stays above the Miller loop over corners and mismatch.
• Active zero: i_M11/i_M9 ≈ (1 + s R_z2 C_gs10)/(1 + s C_d2/g_m10 + s^2 R_z2 C_gs10 C_d2/g_m10). ζ ≈ 0.5 √(C_d2/(g_m10 R_z2 C_gs10)): with g_m10·Rz2 near 0.75 the mirror is just damped; much larger and it rings.

Trade-offs

• Rz2: about 20 kΩ helps; much larger and the mirror rings.
• Km: more units per mirror make the second stage slower through M12, and the loop Cm closes better damped.
• Cm: larger lowers ω_u and raises the phase margin.
• First-stage area: longer input, source and sink units improve common-mode rejection, but using the 8 µm sink geometry in MA1 and MA2 pulled the regulator poles down and made the step ring; the dedicated 4 µm units avoid that tradeoff.
• Rr: 200 kΩ restores regulator gain with the smaller MA1 and MA2 units; lower values lost gain margin, while the verified value keeps MR saturated at every corner.

Testbenches and limits

• Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
• Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
• Step response: A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
• Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
• Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
• Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.

Design variables and defaults

Ports

• inp input
• inn input
• out output
• vdd supply
• vss ground
• ib bias: the reference current, drawn out of this pin

Reference

Z. Yan, P.-I. Mak, M.-K. Law, R. P. Martins, A 0.016-mm² 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With >0.95-MHz GBW, 2013. IEEE Journal of Solid-State Circuits, 48(2):527-540.

The principle: a three-stage amplifier on current-buffer Miller compensation, with a parasitic pole cancelled by an active left-half-plane zero. The arrangement it is built with here - the current buffer as the first stage's regulated cascode, the zero made by gating the second-stage mirror's diode through a resistor, a cross-feedforward second-stage load on the first stage's mirror node and a feedforward output device - and the bias and every size are this library's, for SG13G2 at 1.2 V.