Three-stage op amp, dual active-capacitive feedback

How it works

A three-stage op amp compensated by one capacitor whose current is sensed by a diode and mirrored into both the first and the second stage's outputs: a dual capacitive feedback, acting as Miller capacitors to o1 and to o2 at once. A capacitor on o1 keeps the loop through the sensor damped, a second input pair feeds a small, linear share of the input to the second stage, and the push-pull device feeds o1 forward to the output.

The testbench draws Ib (2.5 µA) out of MB. MT is one copy, the sinks leave 1.5 Ib per cascode, and the sensor runs at 3 Ib: M18 is three copies of M21 and M3 three copies more than M4, which take back the current M19 puts into x1. M17 and M19 are copies of the mirror unit at M7's density, M22 and M23 two cascode units, M5 one, so every twin sits at the same V_DS; the NMOS unit is 8 µm and the PMOS unit 3 µm long, so the sensor copies and their cancellation match closely without the bandwidth cost of the earlier longer sink unit. M12 sets the second stage at 1.9 µA and M14, sixteen copies of M9, the output at 30 µA. Each feedforward side runs at Ib, an eighth of it into the second stage.

Signal path

• First stage (M1, M2, MT, M3, M4, M5, M6, M7, M8): The PMOS pair M1/M2 on the tail MT folds into the sinks M3/M4 and the cascodes M5/M6; the mirror M7/M8 turns the two halves into one output, o1, which falls as inp rises.
• Sensor (Ca, M17, M22, M18, M19): Ca couples out into s, the diode M17, biased by M18 through the cascode M22; M19 copies M17's current into x1, the first stage's mirror diode.
• Dual feedback (M8, M12, M23): The sensed current reaches o1 through M8 and o2 through M12, the second stage's load, both on x1; M23 beside M5 keeps the cascodes at one density, so the sensor's DC current cancels.
• Second stage (M9, M10, M11, M12): M9 into the mirror M10/M11 against M12: a non-inverting stage onto o2. At the default K2 = 1 and Km = 2, stage 2 carries one unit of current, half the full two-unit mirror branch.
• Feedforward pair (M15, M24, M16, M25, MT2, MT3, Rf): M15 (inp) into o2 and M16 (inn) into the diode d2 push o2 the way the main path does. Each side has its own tail and seven more units beside it, M24 and M25, that take the rest of its current to ground, so an eighth reaches the second stage; Rf between the sources keeps that share linear through a step.
• Output stage (M13, M14): M13 on o2 sinks and M14 on o1 sources: a push-pull output, and M14, sixteen copies of M9, is the feedforward path from o1 to the output. Both paths invert, so out follows inp.
• Capacitor on o1 (Cf): Cf from o1 to V_DD lowers the gain of the loop Ca closes, so it crosses below the sensor's and x1's poles; o1 approximately follows V_DD, reducing the capacitor's response to supply changes. Imperfect tracking and other coupling paths still limit supply rejection.

Key relations

• DC gain: A_0 ≈ g_m1 R_o1 · g_m9 R_o2 · g_m13 R_o3. R_o1 is set mostly by the mirror M8, R_o2 and R_o3 by the NMOS M11 and M13, whose V_A is only 2-3 V: the reason those two are long.
• Unity-gain frequency: ω_u ≈ g_m1/C_a. About 3.7 MHz with Ca at 1 pF.
• Dual feedback: i_o2/i_o1 = K_2/K_m. o2 receives half of what o1 does; a path through o2 integrates twice as fast as the main one.
• Feedforward pair: g_m,ff ≈ g_m,side/((1 + g_m,side R_f/2)(1 + K_x)). All of the pair would set the crossover near 11 MHz, where the local loops have no margin; an eighth, kept linear by Rf, adds to the step's damping instead.

Trade-offs

• Cf: without it the loop through the sensor and the mirror oscillates; larger raises the gain margin a little and slows the step.
• Kx: fewer units to ground strengthen the feedforward pair - less overshoot, less gain margin - and send more current into the second stage's mirror, which costs gain.
• Rf: keeps the pair linear through a step; much larger and the pair stops helping the step, smaller and it saturates.
• Kd: the sensor's current must stay twice the cascode current, or the offset grows; its random part falls with the NMOS unit's area.
• Unit-device area: the 8 µm NMOS and 3 µm PMOS units keep the sensor cancellation matched across forty draws; longer sinks add little yield but more capacitance to the cascode and bias nodes.

Testbenches and limits

• Operating point: The amplifier as a unity-gain buffer at its input common mode: the current it draws and where its output settles.
• Open-loop gain: Gain and phase with the loop closed only at DC, through a 1 TH inductor, so the operating point is the buffer's and every frequency sees the open loop.
• Step response: A 200mV step into the unity-gain buffer. Settling requires an output change of 90–110 % of the input step; static offset is reported separately. The 1 % dynamic settling band is around the final output, not a claim of 1 % DC accuracy.
• Supply rejection: A ripple on V_DD, and how much of it reaches the unity-gain buffer's output.
• Common-mode rejection: Equal AC sources on both inputs, one in the feedback path, measure closed-loop common-mode leakage. Its inverse approximates CMRR only where differential loop gain is large.
• Noise: Noise referred to the input of the unity-gain buffer: its density at 1 kHz and its total from 1 Hz to 1 MHz.

Design variables and defaults

Ports

• inp input
• inn input
• out output
• vdd supply
• vss ground
• ib bias: the reference current, drawn out of this pin

Reference

S. Guo, H. Lee, Dual Active-Capacitive-Feedback Compensation for Low-Power Large-Capacitive-Load Three-Stage Amplifiers, 2011. IEEE Journal of Solid-State Circuits, 46(2):452-464.

The dual active-capacitive-feedback compensation (DACFC): one capacitor sensing the output, its current returned through current mirrors to both the first and the second stage's outputs, a capacitor on the first stage's output, a feedforward input pair into the second stage and a feedforward output device. The core amplifier, its bias, the density-matched sensor, the split and the source resistor of the feedforward pair and every size are this library's, for SG13G2 at 1.2 V.