Two-transistor PTAT sensor with a drain shield

How it works

A compact temperature sensor: two copies of one NMOS unit and no bias, with a 3.3 V diode as a drain shield. M1 has its gate on its source, the output, so it passes only its weak-inversion leakage; M2, diode-connected, must carry that same current with only V_out across it, below saturation. In weak inversion a transistor's current is exponential in its source and drain voltages, so the balance settles at V_out ≈ U_T ln(1 + N1/N2): proportional to absolute temperature and independent of the current, the principle of 'CMOS analog integrated circuits based on weak inversion operations'. MS keeps 0.67 V of the supply off M1's thin gate oxide, whose tunnelling would otherwise feed the output at the cold end.

No bias circuit: the current is M1's leakage at V_GS = 0, 0.4 nA at −40 °C, 21 nA at 27 °C and 0.8 µA at 125 °C, and the ideal weak-inversion result is independent of it. Real drain effects and leakage still perturb V_out. The supply sits across MS and M1; MS takes 0.67 V of it.

Signal path

• Drain shield (MS): A diode-connected 3.3 V NMOS, 1 by 1 µm, from the supply to M1's drain: it holds that drain 0.67 V below the supply, so M1's gate oxide sees 0.46 V instead of 1.13 V and tunnels more than ten times less; its own thick oxide has negligible gate tunnelling at these voltages.
• Leakage source (M1): N1 = 7 copies of a single 10 µm finger with the gate on the source: at V_GS = 0 it passes only its subthreshold current, 21 nA at 27 °C, and that current is the cell's.
• Non-saturated diode (M2): One copy, diode-connected: with only V_out, a few U_T, across it, its current carries the factor 1 − exp(−V_out/U_T), and V_out settles where that balances M1.
• Matched units (M1, M2): Both are copies of one 10 by 0.5 µm unit drawn as one finger, seven against one, so the common nominal threshold approximately cancels; mismatch and drain dependence remain.

Key relations

• Output voltage: V_out ≈ U_T ln(1 + N1/N2). both in weak inversion, one threshold: U_T ln 8 = 53.8 mV at 27 °C; M1's barrier lowering at 0.46 V of drain voltage adds about 17 mV, 71.1 mV here
• Temperature slope: dV_out/dT = (k/q) ln(1 + N1/N2). 179 µV/°C ideally, 185 µV/°C here; straight to 1.6 °C from −40 to 125 °C, and to 2.9 °C in the worst of 40 Monte Carlo draws
• Gate tunnelling: I_g,M1 ∝ W_M1 J_EDT(V_DS,M1). M1's gate current from its drain into the output: at −40 °C about 20 pA with the supply on its drain against a few hundred picoamps of leakage, about 1 pA at the shield's 0.46 V
• Cell current: I ≈ N1 I_0 exp(−V_T0/(n U_T)) exp(−V_out (1 − 1/n)/U_T). M1's leakage: a thousandfold over the range and tenfold for a threshold 60 mV low; the ideal output cancels this common current, but real-device effects remain
• Supply: ΔV_out ≈ (N1/(N1 + N2)) σ ΔV_DD / n. σ, M1's drain-induced barrier lowering, steeper at 0.46 V: 4.9 mV over 1.08 to 1.32 V, read as 26 °C

Trade-offs

• N1 and N2: a larger N1/N2 raises V_out and its slope logarithmically and shrinks the supply error in degrees, but M2 then runs at N1/N2 times M1's current density and nears moderate inversion at 125 °C.
• WS and LS (the shield): a smaller shield drops more voltage, cutting M1's tunnelling further and, at 125 °C where the current is largest, its barrier lowering too, which holds the hot end; drop too much and the supply error grows and the hot end falls away. A 1.2 V shield drops too little: Monte Carlo draws still bowed by 15 to 18 °C.
• W (the unit, one finger): a wide single finger leaks more per micron than two narrow ones, which keeps M1's channel ahead of what tunnelling remains; 5 µm fingers bowed up to 6.8 °C in Monte Carlo draws, 10 µm ones 2.9 °C.
• L (the unit): short units have a halo-raised threshold that keeps the hot end in weak inversion; longer ones would cut the barrier lowering but bend at 125 °C.

Testbenches and limits

• Against temperature: The output from -40 to 125 °C at the typical supply: its slope, how far it strays from a straight line, and where that line reaches zero - at -273 °C for an output proportional to absolute temperature.
• Against the supply: The output over the rated supply, 1.08 to 1.32 V, and the temperature error that change would read as.
• Supply rejection: A ripple on V_DD, and how much of it reaches the output, from 1 Hz to 1 GHz.
• Power-up: The supply ramps from 0 to V_DD in 10.0 µs: how long the output takes to come within 1 % of its operating point, and whether it gets there.

Design variables and defaults

Ports

• out output: the PTAT voltage: M1's source, M2's gate and drain
• vdd supply
• vss ground

Reference

E. Vittoz, J. Fellrath, CMOS analog integrated circuits based on weak inversion operations, 1977. IEEE Journal of Solid-State Circuits, 12(3):224-231.

The two-transistor cell and its result: a saturated transistor at V_GS = 0 feeding a non-saturated copy of itself in weak inversion gives V_out = U_T ln(1 + S1/S2), proportional to absolute temperature and independent of the current. The 3.3 V drain shield that keeps the thin-oxide cell from tunnelling, the ratio, the unit and the sizing are this library's.