Resistorless four-transistor PTAT cell

How it works

Four transistors and no resistor give a voltage proportional to absolute temperature. MP1, diode-connected across nearly the whole supply, sets a loop current; MP2 copies it into MN2, whose gate voltage MN1 shares. MN1 has N1 copies of the NMOS unit against MN2's N2, so in saturation it would carry N1/N2 times the current; held to the same current, it drops out of saturation, and in weak inversion its drain voltage, the output, settles where 1 − exp(−V_out/U_T) = N2/N1: V_out ≈ U_T ln(N1/(N1 − N2)), largely independent of current while those conditions hold.

Nothing but MP1 sets the current: its square law across V_DD − V_out, about 50 nA per branch, moving by half over 1.08 to 1.32 V - whose effect on V_out is much smaller because the ideal weak-inversion law cancels common current. All four are 3.3 V devices at a 1.2 V supply, for their threshold; MS1 is a 1.2 V device.

Signal path

• Loop current (MP1, MP2): MP1, long and narrow, sits across V_DD − V_out and sets about 50 nA; MP2 copies it into g.
• Diode (MN2): N2 = 4 copies of the 20 by 4 µm unit, diode-connected and saturated. At about 50 nA, the normalized current I/[N2·(Wn/Ln)] is 2.5 nA; g is about 0.42 V at 27 °C.
• Output device (MN1): N1 = 6 copies at MN2's gate voltage: it can carry MN2's current only below saturation, and its drain voltage, 28.1 mV at 27 °C, is V_out.
• Start-up (MS1): Gate on out, source on g: while the supply comes up out sits high and MS1 feeds g; once the loop runs its gate is 0.4 V below its source and it is off.

Key relations

• Output voltage: V_out ≈ U_T ln(N1/(N1 − N2)). U_T ln 3 = 28.4 mV at 27 °C for N1/N2 = 3/2; about 28.2 mV here; compare tested corner and mismatch results separately
• Temperature slope: dV_out/dT = (k/q) ln(N1/(N1 − N2)). 94.7 µV/°C ideally, 88 µV/°C here; about 0.36 °C from a fitted straight line from −40 to 125 °C
• MN2 saturated: V_GS,MN2 > 5 U_T. 0.17 V at 125 °C: why the pair is 3.3 V devices - their V_GS stays between 0.51 and 0.25 V over the range at about 2.5 nA per unit W/L, where a 1.2 V device's would fall below 0.1 V
• Mismatch: ΔV_out ≈ (N2/(N1 − N2)) ΔV_T/n. the price of a ratio near one: N2/(N1 − N2) is 2 at 3/2, so the pair's threshold mismatch reaches the output about one and a half times over

Trade-offs

• N1 and N2: a ratio nearer one gives a larger V_out and slope, but multiplies the pair's mismatch by N2/(N1 − N2); 2 gives 17.9 mV with half the sensitivity.
• Wp and Lp (MP1, MP2): more current speeds start-up and cuts the start-up device's relative leakage, but moves the pair towards moderate inversion, where V_out follows the current and so the supply.
• Wn and Ln (the NMOS unit): larger units run the pair deeper in weak inversion and match better, at the cost of the gate capacitance MS1 must charge at power-up.

Testbenches and limits

• Against temperature: The output from -40 to 125 °C at the typical supply: its slope, how far it strays from a straight line, and where that line reaches zero - at -273 °C for an output proportional to absolute temperature.
• Against the supply: The output over the rated supply, 1.08 to 1.32 V, and the temperature error that change would read as.
• Supply rejection: A ripple on V_DD, and how much of it reaches the output, from 1 Hz to 1 GHz.
• Power-up: The supply ramps from 0 to V_DD in 10.0 µs: how long the output takes to come within 1 % of its operating point, and whether it gets there.

Design variables and defaults

Ports

• out output: the PTAT voltage: MN1's drain
• vdd supply
• vss ground

Reference

E. Vittoz, J. Fellrath, CMOS analog integrated circuits based on weak inversion operations, 1977. IEEE Journal of Solid-State Circuits, 12(3):224-231.

The principle: a transistor in weak inversion below saturation, made to carry the current of a saturated one at the same gate voltage, settles at a drain voltage that is U_T times a logarithm of their size ratio - proportional to absolute temperature and independent of the current. The four-transistor cell that applies it is credited to the paper; the 3.3 V devices that keep it in weak inversion from -40 to 125 °C at a 1.2 V supply, the start-up device and the sizing are this library's.