Self-biased PTAT generator

How it works

The self-biased loop of a supply-independent bias, run in weak inversion to give a voltage proportional to absolute temperature. M1 is diode-connected; M2, K copies of it, shares its gate with R1 in its source; the mirror M3–M4 forces both to one current. In weak inversion M2 would carry K times M1's current at the same gate voltage, so the voltage across R1 rises until exp(−V_R1/U_T) takes back the factor K: V_R1 ≈ U_T ln K in the weak-inversion approximation; R1 mainly sets current. With both bulks grounded, the common slope factor cancels in this approximation.

Self-biased: the loop settles at the one non-zero current I = U_T ln K / R1, about 100 nA per branch at 27 °C with R1 = 720 kΩ, rising with temperature; the start-up's pull-up MS3 adds about 40 nA. The 1.2 V supply reaches the pair only through M2's drain, one V_SG of M4 below it.

Signal path

• Start-up (MS1, MS2, MS3): Until M1 carries a fifth of its current, MS2 - two copies of M1's own 3.3 V unit - is off and MS3 pulls su up; MS1 then pulls d down into g and drives both branches. Once M1 runs, MS2 holds su at 6 mV and MS1 is off.
• Diode (M1): One 20 by 2 µm unit of the 3.3 V NMOS, diode-connected at about 100 nA: 10 nA per square, weak inversion; its gate voltage g is shared with M2.
• Degenerated copies (M2, R1): K = 16 copies with R1 in their source: to carry M1's current they need V_R1 ≈ U_T ln K less gate-source voltage, and that voltage across R1 is the output.
• Mirror (M3, M4): M4, diode-connected on M2's drain d, and M3 copying it into M1 make the two currents equal and close the loop.

Key relations

• Loop condition: I_M2/I_M1 = K exp(−V_R1/U_T) = 1. weak inversion, both bulks on ground: the gate terms cancel and only the source term is left
• Output voltage: V_R1 ≈ U_T ln K. 71.7 mV at 27 °C for K = 16; 73.3 mV here, the pair's small drain dependence adding the rest
• Temperature slope: dV_R1/dT = (k/q) ln K. 239 µV/°C ideally; about 247 µV/°C here, with 0.38 °C nonlinearity from −40 to 125 °C
• Current: I = U_T ln K / R1. R1 mainly sets current while both devices remain in weak inversion; its value and temperature coefficient can affect real-device departures
• Start-up release: 2 I_M1(V_g) > I_MS3. MS2 takes su away once M1 carries more than half of MS3's 37 nA; a 1.2 V MS2 let go at a trickle of a few nanoamps, where g already sits at 0.2 to 0.35 V, and the loop crawled out on its own for up to 165 µs
• Bulk tied to the source instead: V_R1 = n U_T ln K. larger, but carrying n, which moves with process and temperature, and needing an isolated p-well

Trade-offs

• K (copies of the unit in M2): V_R1 and its slope grow as ln K; area grows as K.
• R1: a larger R1 lowers the current and deepens weak inversion, at the cost of a longer resistor; too small an R1 moves the pair towards the strong-inversion beta multiplier, whose voltage follows mobility.
• Wn and Ln (the NMOS unit, also MS2's): wider units run at a lower current density, deeper in weak inversion; the 3.3 V device is chosen because its drain dependence is small - 1.2 V devices would read 15 °C of error over the supply range.
• MS2 (two copies of M1's unit): matched to M1 it releases the start-up at a fixed fraction of M1's current at every corner, in 10 to 13 µs; smaller copies hold su against MS3 with too little margin, and lose it at cold corners.
• Wp and Lp (the mirror): longer devices copy more exactly across the different drain voltages of M3 and M4.

Testbenches and limits

• Against temperature: The output from -40 to 125 °C at the typical supply: its slope, how far it strays from a straight line, and where that line reaches zero - at -273 °C for an output proportional to absolute temperature.
• Against the supply: The output over the rated supply, 1.08 to 1.32 V, and the temperature error that change would read as.
• Supply rejection: A ripple on V_DD, and how much of it reaches the output, from 1 Hz to 1 GHz.
• Power-up: The supply ramps from 0 to V_DD in 10.0 µs: how long the output takes to come within 1 % of its operating point, and whether it gets there.

Design variables and defaults

Ports

• out output: the PTAT voltage across R1, M2's source
• vdd supply
• vss ground

Reference

B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd, McGraw-Hill, 2016. Ch. 12 'Bandgap References': Sec. 12.4 'PTAT Current Generation' (p. 523), with Sec. 12.2 'Supply-Independent Biasing' (p. 509) and Sec. 12.5 'Constant-Gm Biasing' (p. 524).

The topology - a diode-connected NMOS and a wider one with a resistor in its source, forced to one current by a PMOS mirror - its PTAT result, and the start-up the zero-current state needs. Weak inversion with both bulks on ground, which makes the result U_T ln K with no slope factor in it, the 3.3 V pair and the sizing are this library's.