Sample and hold

How it works

Takes a snapshot of a voltage: while clk is high the switch M1 joins the input to the hold capacitor Ch, which follows it through the switch's on-resistance, and when clk falls Ch keeps the last value. Opening is not clean: part of the channel charge, and the clock step coupled through the gate overlap, land on Ch as a pedestal. An NMOS alone loses strong conduction within a threshold of V_DD; the transmission-gate option adds M2, on clkb, to improve tracking at the top of the range. Leakage and the following stage can change the held voltage.

Nothing is biased: the clock, 0 to 1.2 V, rising at 1 ns and falling about 5 ns later, is the switch's gate drive, and V_in (0.4 V by default) comes from an ideal source. The gate overdrive V_DD − V_in − V_th therefore sets the NMOS's R_on and channel charge. Ground is the hold-capacitor and NMOS-body return. The transmission-gate option also needs an externally supplied clkb complement and vdd for the PMOS well; no on-core clock inverter is included.

Signal path

• Track (M1, M2, Ch): With clk high, M1 (and M2 on clkb, if chosen) conducts; Ch charges towards v_in with τ = R_on·C_h, and the bench counts acquisition to within 1 mV.
• Turn-off (M1, M2): As clk falls the channel empties: about half its charge lands on Ch, and the gate overlap couples the clock step in, a pedestal negative for the NMOS.
• Hold (Ch): With the switch off, Ch keeps the sample; leakage through the off switch and its junctions droops it at I_leak/C_h.

Key relations

• On-resistance: R_on ≈ 1/(µ_n·C_ox·(W/L)·(V_DD − V_in − V_th)). grows without bound as V_in nears V_DD − V_th; M2 covers that end
• Tracking: τ = R_on·C_h. the bench starts Ch at 0 V and counts acquisition to within 1 mV of V_in
• Charge-injection pedestal: ΔV ≈ −W·L·C_ox·(V_DD − V_in − V_th)/(2·C_h). about half of M1's channel charge; M2's holes, in the transmission gate, partly cancel it
• Clock feedthrough: ΔV ≈ −V_DD·C_ov/(C_ov + C_h). the gate–source overlap couples the falling clock onto Ch
• Sampled noise: v_n^2 = kT/C_h. independent of R_on: the noise power halves only when C_h doubles

Trade-offs

• C_hold: a larger capacitor cuts kT/C noise, the pedestal and droop, but lengthens acquisition through the same R_on.
• W NMOS: a wider switch lowers R_on and acquisition time, but injects more channel charge and couples more clock, so the pedestal grows in proportion.
• L: a longer switch only adds R_on and channel charge; minimum length gives the best speed for a given pedestal.
• Switch: the transmission gate tracks up to V_DD, M2 taking over where M1 cuts off, and its opposite charge partly cancels M1's; it needs clkb.

Testbenches and limits

• One sample
• Across the input range: Eleven runs.

Design variables and defaults

Ports

• in input
• out output: the hold node
• clk clock: high tracks, low holds; the clock high level is supplied externally
• clkb clock: transmission-gate option only: externally supplied complement of clk for M2; no inverter is included in the core
• vdd supply: PMOS well connection in the transmission-gate option only; the clock high level is supplied externally, not generated by this pin
• 0 ground: NMOS substrate and hold-capacitor return

Reference

B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed., McGraw-Hill, 2017. Switched-Capacitor Circuits - the MOS sampling switch, charge injection and clock feedthrough.

The two non-idealities this bench measures, and the transmission gate as the standard answer to the first of them.