SAR ADC

How it works

Converts one sampled voltage into an N-bit code by binary search, one comparison per clock. The input is stored as charge on a binary-weighted capacitor array whose common top plate is then left floating. Moving the bottom plates between ground and V_ref redistributes that charge. Ideally, the top plate lands at V_cm − V_in + V_ref·code/2^N; top-plate parasitics reduce the excursion from V_cm. The comparator asks whether that is below V_cm, meaning the trial code is still below the input, and the register keeps or drops each bit, most significant bit first.

Pbt mirrors into the preamplifier's tail the 20 µA the bench drives into pin ib through Pbd; each input device takes 10 µA through 30 kΩ of p+ poly, R1 and R3 or R2 and R4, which holds the latch's inputs near 0.9 V. The latch draws charge only as it decides. V_ref sets the full scale and supplies the bit drivers, V_cm is both the top plate's sampling level and the comparator's reference, and samp and clk, 100 MHz by default, set the timing.

Signal path

• Sample (St, Si0..SiN-1, Sit): While samp is high, St holds the top plate at V_cm and every bottom plate sits on V_in; St opens two gate delays before the others (bottom-plate sampling).
• MSB trial (Sd0..SdN-1, B0..BN-1, Sgt): The bottom plates leave V_in for their drivers, Ct's for ground. With the MSB preset, an ideal array puts the top plate at V_cm + V_ref/2 − V_in. Physical top-plate capacitance attenuates its displacement from V_cm; switching adds further error.
• Compare (P1, P2, R1..R4, Mt, M1..M10, Ls, Lr): While clk is low, the preamplifier, a gain of about 5, and the StrongARM latch decide whether V_cm is above the top plate, meaning keep the bit; the NOR latch holds the answer.
• Register (T0..TN-1, K0..KN-1, F0..FN-1, O0..ON-1): Each rising clk edge stores the decision in that bit's flip-flop and passes the token down; the OR gates put the next trial on the array beside the kept bits.
• End of conversion (Tend): N rising edges after sampling the token reaches Tend and eoc rises; the top plate then sits within one LSB below V_cm, and d0..dN-1 hold the code.

Key relations

• Top plate in each trial: v_top ≈ V_cm + α·(V_ref·code/2^N − V_in). α is the array capacitance divided by total top-plate capacitance, about 0.94 here; α = 1 gives the ideal equation. Charge injection and comparator kickback add further errors. A trial bit is kept when v_top < V_cm.
• LSB: LSB = V_ref/2^N. 18.75 mV with V_ref = 1.2 V at 6 bits; the selected conversion is checked against the published ±1 LSB requirement. This single input point does not establish full-code ADC linearity.
• Conversion time: t_conv = N·T_clk. nominal timing calculation: one trial per clock after sampling, 60 ns at 6 bits and 100 MHz; this number is not a measured EOC delay
• Bottom-plate settling: T_clk/2 ≥ τ·ln(2^(N+1)). settle to half an LSB before the latch fires; drivers and switches scale with C_k so τ is shared
• Comparator offset: σ_os^2 ≈ σ_P^2 + σ_R^2 + (σ_L/A_p)^2. The preamplifier pair, loads and latch contribute input-referred mismatch; their uncorrelated variances add approximately. Comparator offset shifts code boundaries. The ideal sampled rms noise √[kT/(2^N·C_u)] is about 57 µV at the defaults; this is a calculation, not a transient-noise measurement.

Trade-offs

• Resolution: each extra bit halves the LSB, doubles the array and its switching energy, adds a clock cycle, and asks more of the capacitor matching.
• C_unit: a larger unit lowers kT/C noise but raises the energy per conversion and slows each bit's settling through the same drivers.
• Clock: faster shortens the N-cycle conversion, but each half period must still settle the bottom plates and let the latch resolve the closest trial.
• Switch nMOS width: wider switches track and settle faster but add channel charge and capacitance; bottom-plate sampling leaves only St's input-independent charge, an offset.

Testbenches and limits

• Conversion: One conversion with every device simulated: about 10 s in the browser.

Design variables and defaults

Ports

• vin input: the input, sampled onto the bottom plates
• vcm bias: the top plate's level while sampling, and the comparator's reference
• vref bias: what the bit drivers switch the bottom plates to: the full scale
• ib bias: 20 uA into the preamplifier's bias mirror
• clk clock: high: the comparator precharges; each rising edge ends a trial
• samp clock: high: track the input; its falling edge samples it
• d0..dN-1 output: the result, valid once eoc rises
• eoc output: end of conversion
• vdd supply

Reference

J. L. McCreary and P. R. Gray, All-MOS charge redistribution analog-to-digital conversion techniques - Part I, IEEE Journal of Solid-State Circuits, vol. SC-10, no. 6, 1975. the binary-weighted charge-redistribution array and its sample / redistribute sequence.

The array, its sample-then-redistribute sequence, and the charge-conservation result every trial is checked against: v(top) = V_cm - V_in + V_ref*code/2^N.