SAR ADC, monotonic switching

How it works

Converts a differential input, V_ip − V_in, into N bits with one-way capacitor switching. Both inputs are sampled on the top plates of two binary arrays whose switched bottom plates start on V_ref; the most significant bit is decided on the samples as they are, and each later decision pulls one capacitor of the higher side from V_ref to ground, moving that plate down by approximately V_ref·C_k/C_side. The ideal top plates only fall during conversion, avoiding charge returned to V_ref by upward steps. N bits need N − 1 switched capacitor weights per side, plus a termination capacitor.

Pbt mirrors into the preamplifier's tail the 20 µA the bench sinks from pin ib through Pbd, and 20 kΩ loads to ground keep its outputs below 0.4 V, where the latch's PMOS inputs work at every corner - even when, with the top plates at 0.6 V, the tail has almost no headroom. V_ref is where every switched bottom plate starts and the drivers' supply; samp's falling edge samples, and clk, 100 MHz by default, paces one decision per period.

Signal path

• Sample (Sp, Sn, CP0..CPN-2, CN0..CNN-2, CPt, CNt): While samp is high, transmission gates put vip on topp and vin on topn with every switched bottom plate on V_ref; samp's fall leaves both top plates floating.
• MSB without switching (Xcmp): The first comparison is made on the sampled inputs directly: topp above topn is a 1 for the MSB, and no capacitor has moved yet.
• One side down (LP0..LPN-2, LN0..LNN-2, DP0..DPN-2, DN0..DNN-2): After bit k+1, capacitor k of the higher side (P after a 1, N after a 0) drops from V_ref to ground, pulling that top plate down.
• Comparator (Pbt, P1, P2, R1..R4, Mt, M1..M10, Ls, Lr): A PMOS preamplifier, 20 kΩ loads to ground, works down to inputs at ground; a StrongARM with a PMOS input pair decides from its outputs, below 0.4 V; the NOR latch holds each answer.
• Register (T0..TN-2, H0..HN-1, K0..KN-1, F0..FN-1): A 1 shifts down the thermometer s_k each clock and stays, marking decided bits; each flip-flop loads the decision on the edge ending its turn.

Key relations

• LSB: LSB = 2·V_ref/2^N. the differential range is ±V_ref: 37.5 mV at 6 bits and 1.2 V
• Step after bit k+1: ΔV_top = V_ref·2^k/2^(N−1). on the higher side only: V_ref/2 first, V_ref/4 next; top-plate parasitics shrink each alike
• Array per side: C_side = 2^(N−1)·C_u. half the conventional array, because the MSB is decided before anything switches
• Common-mode fall: ΔV_cm ≈ −(V_ref/2)·(1 − 2^(1−N)). each step moves one side, so the common mode falls half as far: 0.6 V to near ground by default
• Nominal conversion interval: t_conv = N·T_clk. one scheduled decision per clock after sampling: 60 ns at 6 bits and 100 MHz; calculated from timing, not a measured EOC delay

Trade-offs

• Resolution: each extra bit halves the LSB, doubles both arrays, adds a clock cycle and ends the conversion with the common mode nearer ground.
• C_unit: a larger unit lowers kT/C noise and dilutes the top-plate parasitic, shrinking the gain error, but raises switching energy and settling time.
• Sampling switch nMOS width: wider gates track faster, but their channel charge lands on the sampled top plates and their capacitance shrinks every step alike.
• Clock: faster shortens the N-cycle conversion, but each half period must settle the switched plate and let the latch decide at a falling common mode.

Testbenches and limits

• Conversion: One conversion with every device simulated: about 10 s in the browser at 6 bits.

Design variables and defaults

Ports

• vip input (+): sampled onto the P array's top plate
• vin input (-): sampled onto the N array's top plate
• vref bias: the level every bottom plate starts on, and the drivers' supply
• ib bias: the bench sinks 20 uA from it: the preamplifier's bias
• clk clock: high: the comparator precharges; each rising edge ends a trial
• samp clock: high: the top plates track the inputs; its falling edge samples them
• d0..dN-1 output: the result, valid once eoc rises
• eoc output: end of conversion
• vdd supply

Reference

C.-C. Liu, S.-J. Chang, G.-Y. Huang and Y.-Z. Lin, A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure, IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 731-740, 2010. the monotonic switching procedure: top-plate sampling, the MSB decided without switching, one side switched down per bit.

The procedure, the halved array, the falling common mode and what it asks of the comparator, and the switching-energy argument.