Sigma-delta modulator (first order)

How it works

Turns a slowly varying input into a stream of one-bit decisions whose long-term density of ones approaches V_in/V_DD. An integrator accumulates the difference between the input and a one-bit DAC, and a comparator on the integrator's output picks the next decision each clock. The discrete-time DAC feeds back V_DD or ground directly; the continuous-time circuit uses the complemented bit and V_cm = V_DD/2. The integrator stays bounded only when average feedback balances the input. In the ideal first-order model, quantisation error is differentiated, reducing its low-frequency content. A digital decimation filter averages sampled bits, not the analog area of their voltage pulses.

Ib, 80 µA by default, flows into Mb, four 10/2 µm units; the integrator's tail Mt, four units, copies it, its second stage M6, sixteen units, four times over, and the comparator's tail MQT, one unit, a quarter of it, all saturated. V_cm, V_DD/2 from the bench, is the integrator's reference and the comparator's threshold. The period is 20 ns: two non-overlapping 9 ns phases in discrete time, one flip-flop edge in continuous time.

Signal path

• Sample (phase 1) (S1n, S1p, S2n, S2p, CS): In phase 1, S1 puts V_in on C_s's left plate and S2 holds the right one at V_cm, storing C_s·(V_in − V_cm).
• DAC and transfer (phase 2) (GP, GN, MDP, MDN, S4n, S4p): In phase 2 MDP or MDN puts the left plate at vdd (q = 1) or ground, S4 joins the right to sum, and C_s·(V_in − V_dac) moves into C_i.
• Integrator (M1, M2, M3, M4, M5, M6, CC, RZ, CI): M1–M6 form a two-stage Miller amplifier (CC, RZ) that holds sum at V_cm, so each period steps v_o by (C_s/C_i)·(V_in − V_dac); it must settle within phase 2.
• Quantiser (MQT, MQ1, MQ2, MQ3, MQ4, IQ, FQ): MQ1–MQ4 compare v_o with V_cm, IQ squares the result, and FQ, clocked as phase 1 ends, holds q for the DAC: q = 1 when v_o is above V_cm.
• Continuous-time option (RIN, RDAC, GD): With Loop filter at continuous time, RIN and RDAC feed V_in and GD's complement of q into sum all the time; the comparator's inputs swap, and FQ samples on clk.
• Reset (SRn, SRp): SRn and SRp short C_i through the first period, so each run starts with v_o at V_cm, while rstb holds FQ cleared.

Key relations

• Density of ones: n_1/N ≈ V_in/V_DD. for a settled, bounded loop and a constant input; finite counts only approximate the long-term balance. At the nominal default, 24 ones in 64 represent 0.45 V.
• Integrator step: Δv_o = (C_s/C_i)·(V_in − V_DD·q). discrete time, assuming ideal charge transfer and settling. In continuous time, dv_o/dt = −(V_in − V_DD·q)/(R·C_i) when V_cm = V_DD/2; the comparator polarity reverses too. C_s/C_i and T/(R·C_i) are both 1/4 by default.
• Noise transfer: NTF(z) = 1 − z^(−1). the normalized ideal first-order model: the input passes delayed and low-frequency quantisation error is differentiated, rising approximately 20 dB per decade. This is a teaching model, not an extracted transfer function of either transistor circuit.
• In-band quantisation noise: P_q ≈ (Δ^2/12)·(π^2/3)·OSR^(−3). ideal additive-white-quantisation-error approximation, with Δ = V_DD and OSR the sampling rate divided by twice the signal bandwidth; each doubling of OSR predicts about 9 dB. A real first-order bitstream can contain tones, so the finite-record result need not follow this exactly.
• Averaging: δV = V_DD/N. spacing of the values available from an N-bit count; this is not a guarantee of total input accuracy or effective resolution

Trade-offs

• C_s (discrete time): a larger C_s lowers kT/C noise and enlarges each step C_s/C_i, but loads the amplifier, which must still settle within phase 2.
• C_i: a larger C_i shrinks the integrator's swing and keeps the amplifier linear, at the cost of area and a smaller signal at the comparator.
• Amplifier bias: more current settles C_s's charge sooner in phase 2 but needs more V_DS for the tail below inputs at V_cm; less saves power until the integrator is still drifting when the comparator decides.
• Loop filter: discrete time rests on C_s/C_i and needs input anti-alias filtering. Continuous-time integration attenuates some out-of-band input before sampling, but does not guarantee enough alias rejection; its dynamics depend on R·C_i and DAC timing.
• Integration: the bench supplies p1/p1b and p2/p2b in discrete time, clk in continuous time, and rst/rstb in both. A physical implementation needs the appropriate clock, non-overlap and reset generation, plus bias and V_cm circuits; their nonideal behavior is not established by ideal bench sources.

Testbenches and limits

• A DC input: 64 clock periods with every transistor simulated: 10-15 s in the browser.
• A sine, and its spectrum: 128 clock periods with every transistor simulated: 15-20 s in the browser.

Design variables and defaults

Ports

• vin input
• vcm bias: the middle of the range, V_DD/2 (the bench derives it from the supply): the integrator's reference
• bn bias: the amplifiers' bias: the bench gives a current into Mb
• p1 clock: discrete time: phase 1, sampling (p1b its complement)
• p1b clock: discrete time: externally supplied complement of p1; also clocks the decision flip-flop
• p2 clock: discrete time: phase 2, integrating (p2b its complement)
• p2b clock: discrete time: externally supplied complement of p2
• clk clock: continuous time: the flip-flop's clock
• rst clock: high through the first period: C_i shorted (rstb clears the flip-flop)
• rstb clock: externally supplied complement of rst: active-low flip-flop reset and integrator reset-switch control
• q output: the bitstream
• vdd supply
• 0 ground

Reference

S. Pavan, R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, 2nd ed., Wiley-IEEE Press, 2017. The first-order modulator - its loop, noise shaping and tones - and its discrete-time and continuous-time loop filters.

The loop, the result that the density of ones follows the input, the 20 dB/decade shaping of the quantisation noise, and the two ways of building the integrator.

• T. Chan Carusone, D. A. Johns and K. W. Martin, Analog Integrated Circuit Design, 2nd ed., 2012