StrongARM latch comparator

How it works

Decides in one clock phase which of two inputs is higher and resolves the answer to full logic levels, with no intentional static bias path; physical device leakage remains. With clk low, M7–M10 precharge both outputs and both internal drains to V_DD; when clk rises, the input pair turns V_id into a small current imbalance, and the cross-coupled inverters M3–M6 amplify it by positive feedback, approximately exponentially with time constant τ = C/g_m, until one output reaches ground. A small V_id means a long decision, possibly unfinished in time: metastability.

No intentional bias current: Mtail is a switch driven by clk. The large current pulses occur during evaluation and precharge; the bench also measures the residual supply current at the end of the transient, without assuming zero leakage. The vdd and ground ports power the latch and provide its body connections. The bench holds inp and inn at V_CM ± V_id/2, 0.8 V and 10 mV by default, and loads each output with C_out, 5 fF.

Signal path

• Precharge (M7, M8, M9, M10): While clk is low M7–M10 pull outp, outn, dip and din to V_DD and Mtail is off, so every decision starts balanced without an intentional DC conduction path. Device leakage is not zero.
• Input integration (Mtail, M1, M2): When clk rises, Mtail turns on and M1 and M2 discharge dip and din at rates set by inp and inn, turning V_id into a growing voltage difference.
• NMOS regeneration (M3, M4): Once dip and din fall about V_thn below V_DD, M3 and M4 conduct and discharge outn and outp; their crossed gates start amplifying the difference.
• Full regeneration (M5, M6): When an output falls a PMOS threshold below V_DD, M5 and M6 join: the cross-coupled inverters drive outn to ground when inp > inn and restore outp to V_DD.

Key relations

• Regeneration: ΔV(t) = ΔV_0·e^(t/τ), τ = C/g_m. C is an output node's capacitance, g_m the cross-coupled pair's
• Decision time: t_dec ≈ t_0 + τ·ln(ΔV_out/(A_0·V_id)). A_0 is the input phase's gain; each decade less overdrive adds τ·ln 10 ≈ 2.3τ
• Offset: σ_Vos ≈ A_Vt/√(W·L). Pelgrom mismatch of M1 and M2; the latch pair's own adds, divided by A_0
• Kickback: Δv_in ≈ C_gd·Δv_d/(C_gd + C_src). dip and din swing by about V_DD; the bench's ideal sources absorb it, a floating capacitor would not

Trade-offs

• C_out: τ = C/g_m grows in proportion to the load, slowing every decision and widening the range of overdrives left undecided in time.
• W latch N and W latch P: widening them raises g_m, but their own capacitance loads the outputs, so τ shrinks less than proportionally.
• W input pair: a wider pair lowers offset (σ ∝ 1/√(W·L)) and raises the integration gain, but loads the inputs and raises kickback through C_gd.
• V_CM: a higher common mode discharges dip and din sooner, shortening the decision, but leaves less integration gain, so the latch pair's offset matters more.

Testbenches and limits

• One decision
• Decision time vs overdrive: Eight positive-overdrive runs, 1–200 mV. Every requested point is retained; wrong-polarity or unresolved decisions have no valid decision time.

Design variables and defaults

Ports

• inp input (+)
• inn input (-)
• clk clock: low precharges, high evaluates
• outp output
• outn output
• vdd supply: latch and precharge supply, including PMOS well connections
• 0 ground: tail-source and NMOS substrate return

Reference

B. Razavi, The StrongARM Latch [A Circuit for All Seasons], IEEE Solid-State Circuits Magazine, vol. 7, no. 2, 2015. the topology, its four phases, and the regeneration time constant.

The circuit as drawn here, and the result that decision time grows as ln(1/V_id) with a time constant tau = C/gm.

• J. Montanaro et al., A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor, IEEE Journal of Solid-State Circuits, vol. 31, no. 11, 1996