Designs › Amplifier stages › Followers
Super source follower
A source follower with local feedback that lowers its output resistance. A second transistor adjusts the current available to the load, keeping the output steadier. A compensation capacitor controls the loop's response; changing the load requires another stability check.
How it works
M3 supplies an approximately fixed current to follower M1. Changes at M1's drain drive M2, which sinks more or less of that current at the output. This local loop reduces output resistance by its gain. Cc compensates the loop for the chosen capacitive load.
The testbench draws Ib, 10 µA, out of the ib pin; M3, five copies of MB, feeds 50 µA into x, and with no load M2 sinks all of it: 60 µA from the supply. The input sits at 0.74 V and the output follows about 0.41 V lower. M1's drain sits at V_GS2, about 0.74 V - M2 is short, narrow and strongly inverted so that its V_GS is large - which leaves both M1 and M2 saturated with margin at every corner.
Signal path
- Follower (M1): Gate on in, source on out: with its current fixed by M3 its V_GS barely changes, and out follows in a V_GS lower.
- Current source (MB, M3): Ib, drawn out of the ib pin, sets the diode MB; M3, K copies of it, feeds K·Ib into x, the follower's drain.
- Feedback device (M2): Gate on x, drain on out: when a load pulls on out, M1's current would change; x swings instead, and M2 takes up the difference.
- Compensation (Cc): On x, it makes the loop's first pole dominant, so the loop crosses over before the output pole, (g_m1 + g_mb1)/C_L, turns its phase.
Key relations
- Output resistance:
R_out ≈ 1/[(g_m1 + g_mb1) · g_m2 (r_o1 ∥ r_o3)]. a plain follower's 1/(g_m1 + g_mb1), about 1.4 kΩ, divided by the loop's gain: 120 Ω at tt, under 200 Ω at every corner - Gain:
A_v ≈ g_m1/(g_m1 + g_mb1). M1's bulk is on ground, so the body effect still costs about 1.25 dB: the loop lowers R_out, not this - Output window:
V_DSAT,2 < V_out < V_GS2 − V_DSAT,1. M1's drain sits at V_GS2, so a large V_GS2 lifts the ceiling - Closed-loop response:
H(s) = A_v (1 + s/ω_z) ω_n²/(s² + 2ζω_n s + ω_n²), ω_z = g_m2/C_c. with ω_n² = (g_m1 + g_mb1) g_m2/(C_L C_c): the zero sits at ω_n/(2ζ), below ω_n, so the response always peaks a little - Damping:
ζ ≈ ½ √[(g_m1 + g_mb1) C_c/(g_m2 C_L)]. above one with 3 pF: the step overshoots about 6 %, the gain peaks under 0.5 dB
Trade-offs
- Compensation (Cc): more generally reduces peaking and overshoot at a bandwidth cost. The numerator zero can cause overshoot even with overdamped poles, but it does not impose a fixed few-percent floor; check the response at the chosen load.
- Follower current (K): more current raises g_m1 and g_m2 and lowers R_out as 1/I, at more supply current and a larger V_GS2.
- Feedback device (W2, L2): wider raises g_m2 and lowers R_out, but lowers V_GS2 and with it the window's ceiling.
- Input level (VIN): the window is fixed by M1 and M2 and the bias belongs in it, a little high: hot corners push the output up while the ceiling falls, and the slow ones squeeze M2 from below.
Testbenches and limits
- Operating point: The stage with its input at its bias level: the current it draws and where its output sits.
- DC transfer: The input swept across the stage's range: the output, the gain against the output, and the output range - how far the output moves before that gain falls 1 dB from its peak.
- Gain and bandwidth: Gain and phase at the bias point, into the circuit's load.
- Output resistance: A 1 A AC current into the output with the input held at its bias: the voltage it makes is the output impedance.
- Step response: A 50mV step at the input around its bias level: how fast the output follows, and whether it rings.
| Bench | Figure | Limit |
|---|---|---|
| Operating point | Supply current | ≤ 70 µA |
| DC transfer | Output range | ≥ 350 mV |
| Gain and bandwidth | Gain at the bias point | ≥ -2 dB |
| Gain and bandwidth | Bandwidth, -3 dB | ≥ 50 MHz |
| Gain and bandwidth | Peaking | ≤ 1 dB |
| Output resistance | Output resistance | ≤ 200 Ω |
| Step response | Overshoot | ≤ 10 % |
Design variables and defaults
| Variable | Default |
|---|---|
| Reference current | 10 µA |
| Follower current, in Ib | 5 |
| W PMOS unit (MB, M3) | 6 µm |
| L PMOS unit | 1 µm |
| W follower (M1) | 16 µm |
| L follower | 1 µm |
| W feedback device (M2) | 1 µm |
| L feedback device | 130 nm |
| Compensation capacitor | 3 pF |
| Load capacitance | 1 pF |
| Input level | 740 mV |
Ports
ininputoutoutputvddsupplyvssgroundibbias: the reference current, drawn out of this pin
Reference
P. R. Gray, P. J. Hurst, S. H. Lewis, R. G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Wiley, 2009. Sec. 3.4.4 'The Super Source Follower' (p. 212).
The topology - a follower whose drain current is held by a current source, and a feedback device driven from its drain that sinks the load's current - and the result that the loop divides the output resistance by its gain. The compensation at the follower's drain, the bias and the sizing are this library's, for SG13G2 at 1.2 V.
IHP SG13G2 130 nm. Simulations run in your browser; open the workbench to run this design's benches and change its variables.