NMOS track-and-hold, dummy switch

How it works

While clk is high, the NMOS switch M1 joins the input to the hold capacitor C_H. When clk falls, M1 releases channel charge and couples part of the clock step onto the held voltage. The half-size dummy MD has both ends on the hold node and turns on through the inverted clock. Its channel charge and clock coupling oppose M1's error, but cancellation is approximate. The default uses a 7 µm main switch, a 3.5 µm dummy and a 1.55 pF hold capacitor: wider switches improve endpoint tracking, while the larger capacitor limits residual pedestal. The inverter and clock timing are unchanged.

No separate bias current is required. The bench drives M1's gate from 0 to V_DD with a 100 ps fall, and the on-core inverter makes clkb from the same supply. The supported input range stops at 40 % of V_DD, or 0.48 V at 1.2 V. Wider switches reduce resistance but do not remove the NMOS headroom limit.

Signal path

• Track (M1, CH): With clk high, M1 conducts and C_H follows the input. M1 is two copies of the 3.5 µm unit at the default sizing. Its on-resistance rises toward the upper input limit as gate overdrive falls.
• Sampling instant (M1): As clk falls, some of M1's channel charge reaches C_H and its gate overlap couples a falling-clock step. The charge split depends on the input level, clock slew and source impedance.
• Cancellation (MD, MI1, MI2): MI1–MI2 invert clk into clkb. Turning on the half-size dummy draws charge from C_H, while its two overlaps couple a rising-clock step. Both oppose the main switch's error, without guaranteeing exact cancellation.
• Hold (CH): With M1 off, C_H holds the sample. Off-state, gate and junction leakage gradually change its voltage; the leakage bench estimates the worst droop as current divided by C_H.

Key relations

• On-resistance: R_on ≈ 1/(µ_n C_ox (W/L)_M1 (V_DD − v_in − V_th(v_in))). First-order trend: resistance increases as gate overdrive falls and body effect raises the threshold. Use the model sweep for numerical values.
• Injected charge: ΔV_M1 ≈ −(W L C_ox)_M1 (V_DD − v_in − V_th)/(2 C_H) − C_ov,M1 V_DD/C_H. Assumes half the main switch's channel charge reaches the held capacitor; actual partition and clock feedthrough depend on the circuit and timing.
• Dummy: ΔV_MD ≈ +(W L C_ox)_MD (V_DD − v_out − V_th)/C_H + 2 C_ov,MD V_DD/C_H. MD = M1/2 and v_out = v_in: equal and opposite, if M1's charge splits evenly
• Ideal sampled thermal-noise estimate: v_n^2 = kT/C_H. For ideal settled sampling at 27 °C on the default 1.55 pF, sqrt(kT/C_H) is about 51.7 µV rms. This is an analytic estimate, not thermal noise measured by these deterministic simulations.

Trade-offs

• W (the switch unit): wider lowers R_on, but adds switch area, clock loading and possible leakage. Both main and dummy widths increase together to preserve the 2:1 ratio.
• C_H: a larger capacitor reduces the ideal kT/C noise estimate and converts a given residual charge or leakage current into less voltage error. It costs area and slows tracking at fixed switch resistance.
• The defaults increase W from 2 to 3.5 µm and C_H from 1 to 1.55 pF. This balances bandwidth at the exact input-range endpoint against pedestal and leakage, without relaxing any limit.
• Wi (the inverter): complementary-clock delay affects cancellation. If the dummy turns on while M1 still conducts, part of its charge comes from the input instead of the hold capacitor.
• Dummy: turning it off leaves a plain NMOS track-and-hold. Compare the injection bench to see the resulting pedestal rather than assuming a fixed voltage error.

Testbenches and limits

• On-resistance: The switch closed, its input swept over its signal range, 0 % of V_DD to 40 % of V_DD, and its output held 10 mV below it: the current through it gives its on-resistance at every level.
• Pedestal: The control falls in 100 ps after tracking. Pedestal is checked at seven sampled levels including 0% and 40% VDD; this is a sampled maximum, not a continuous-range bound.
• Off leakage: The switch open, its input at one end of its range and then the other, its output swept from 0 % of V_DD to 40 % of V_DD: the current that reaches the output with a real voltage across the switch.
• Track bandwidth: The closed switch drives its hold capacitance at seven sampled levels including 0% and 40% VDD. Every level must produce a finite bandwidth; missing crossings are not dropped.

Design variables and defaults

Ports

• in input
• out output: the hold node
• clk clock: high tracks, low holds
• vdd supply: the inverter's supply
• vss ground

Reference

B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd, McGraw-Hill, 2016. Switched-capacitor circuits: the MOS sampling switch, charge injection and clock feedthrough, and the dummy switch that cancels them.

The track-and-hold and its errors, and the dummy switch: half the switch's width, shorted, clocked by the complement, so that the charge and the overlap step it draws from the hold node match what the switch leaves there. The inverter that makes the complement, and the sizing, are this library's.