Threshold-difference voltage reference

How it works

A voltage reference from two transistors of different threshold and about 0.28 nA at the nominal condition. M1, nine copies of a 1.2 V NMOS unit with the gate on the source, passes only its subthreshold current; M2, a diode-connected 3.3 V NMOS whose threshold is about 0.3 V higher, must carry the same current, which fixes its V_GS, the output. In weak inversion that V_GS is the threshold difference over n plus U_T times a logarithm of the size ratio: the first falls with temperature, the second rises, and the copy count sets them to cancel. MS, a 3.3 V diode above M1, keeps the supply off M1's thin gate oxide, whose tunnelling would otherwise feed the picoamp node at the cold end.

Nothing sets the current but M1's leakage at V_GS = 0, from 4 pA at −40 °C to 15 nA at 125 °C; the simplified weak-inversion law sets V_ref from thresholds and size ratio. Real drain and leakage effects still perturb it. The node is so weakly driven that it charges in 35 µs at 27 °C and 1.8 ms at −40 °C.

Signal path

• Drain shield (MS): A diode-connected 3.3 V NMOS, 2 by 1 µm, from the supply to M1's drain: it holds that drain 0.55 V below the supply, so M1's gate oxide sees 0.31 V instead of 0.85 V and has much less gate tunnelling into V_ref; the shield's thick-oxide gate leakage is negligible at these voltages.
• Leakage source (M1): N1 = 9 copies of a 1 by 2 µm 1.2 V unit, gate and source on V_ref: at V_GS = 0 its subthreshold current is the cell's only bias, 0.28 nA at 27 °C.
• Reference diode (M2): A 3 by 2 µm 3.3 V NMOS, gate and drain on V_ref: it settles at the V_GS that carries M1's current, and that V_GS is the output, 345 mV.

Key relations

• Reference voltage: V_ref ≈ (V_T0,M2 − V_T0,M1)/n + U_T ln(S_M1 I_0,M1 / (S_M2 I_0,M2)). simplified weak inversion with a common slope factor; M1's raised source introduces body effect
• Temperature coefficient: dV_ref/dT ≈ d(V_T0,M2 − V_T0,M1)/dT / n + (k/q) ln(S_M1 I_0,M1 / (S_M2 I_0,M2)). the 3.3 V threshold falls faster; N1 = 9 balances the two: 29 ppm/°C from −40 to 125 °C, at most 110 ppm/°C over 40 Monte Carlo draws
• Process spread: σ(V_ref) ≈ σ(V_T0,M2 − V_T0,M1)/n. the two thresholds come from separate implants and move apart from die to die: σ 30 to 35 mV over the draws, which a copy of M1, 3.5 mV, does not close
• Cell current: I ≈ N1 I_0,M1 exp(−V_T,M1(V_ref)/(n U_T)). M1's leakage, V_T,M1 raised by the body effect at V_SB = V_ref
• Supply: ΔV_ref ≈ σ_M1 ΔV_DD / n. M1's drain-induced barrier lowering, steeper at the shield's 0.31 V: 5.6 mV over 1.08 to 1.32 V, 6.7 %/V

Trade-offs

• N1 (copies of M1's unit): near the default, an added copy shifts the output by a few millivolts and changes its slope; the steps are logarithmic, not constant: the trim, since the 1.2 V and 3.3 V thresholds move apart over process and the slow and fast corners need a copy more or less.
• W2 and L2 (M2): the same balance from the other side - a larger M2 lowers V_ref and its slope with the current nearly unchanged.
• WS and LS (the shield): a smaller shield holds M1's drain lower, cutting its tunnelling further but steepening the barrier lowering that passes the supply to V_ref; without it, draws that leaked several times less than typical bowed up by 20 to 25 mV at −40 °C.
• L1 (M1's unit): longer cuts the barrier lowering, at the cost of M1's leakage and so of the start-up time.

Testbenches and limits

• Against temperature: The output from -40 to 125 °C at the typical supply: its level, and how much it moves - the temperature coefficient, by the box method.
• Against the supply: The output over 1.08–1.32 V: line regulation uses the magnitude of its normalized endpoint change. The signed voltage change is retained separately.
• Supply rejection: A ripple on V_DD, and how much of it reaches the output, from 1 Hz to 1 GHz.
• Power-up: The supply ramps from 0 to V_DD in 10.0 µs: how long the output takes to come within 1 % of its operating point, and whether it gets there.

Design variables and defaults

Ports

• out output: V_ref: M2's gate and drain
• vdd supply
• vss ground

Reference

M. Seok, G. Kim, D. Blaauw, D. Sylvester, A portable 2-transistor picowatt temperature-compensated voltage reference operating at 0.5 V, 2012. IEEE Journal of Solid-State Circuits, 47(10):2534-2545.

The topology: a transistor at V_GS = 0 whose leakage is the only bias, feeding a diode-connected thick-oxide transistor, their threshold difference falling with temperature against a logarithm of their size ratio rising with it. The paper's top device is a native NMOS; SG13G2 has none, so a 1.2 V core NMOS takes its place. The 3.3 V drain shield that keeps its thin oxide from tunnelling, the copy count that cancels the temperature coefficient and the sizing are this library's.

• E. Vittoz, J. Fellrath, CMOS analog integrated circuits based on weak inversion operations, 1977